用VHDL编写的计数器,能通过语法检测,但不可以综合,哪里出错了?提示 Variable i :std_logic_vector (7 downto 0) 中的“i” 有以下错误：“Signal i cannot be synthesized,bad synchronous description.The description style yo

用VHDL编写的计数器,能通过语法检测,但不可以综合,哪里出错了?提示 Variable i :std_logic_vector (7 downto 0) 中的“i” 有以下错误：“Signal i cannot be synthesized,bad synchronous description.The description style yo
用VHDL编写的计数器,能通过语法检测,但不可以综合,哪里出错了?
提示 Variable i :std_logic_vector (7 downto 0) 中的“i” 有以下错误：
“
Signal i cannot be synthesized,bad synchronous description.The description style you are using to describe a synchronous element (register,memory,etc.) is not supported in the current software release.”
Library ieee;
Use ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
Entity counter is
port(clk ,cw,increment,reset:in std_logic;
led :out std_logic_vector (7 downto 0) );
End counter;
Architecture counter of counter is
Begin
Process(clk ,cw,increment,reset)
Variable i :std_logic_vector (7 downto 0);
Begin
If(reset'event and reset = '1') then
i := "00000000";
elsIf(clk'event and clk = '1') then
If(increment'event and increment = '1') then
If(cw = '1') then
i := i + 1;
elsIf(cw = '0') then
i := i - 1;
End if;
Else null;
End if;
End if;
led

用VHDL编写的计数器,能通过语法检测,但不可以综合,哪里出错了?提示 Variable i :std_logic_vector (7 downto 0) 中的“i” 有以下错误：“Signal i cannot be synthesized,bad synchronous description.The description style yo
oh my god!你连用了三个时钟上升沿,难怪会说你bad synchronous description.
程序改正如下：
Library ieee;
Use ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
Entity counter is
port(clk ,cw,increment,reset:in std_logic;
led :out std_logic_vector (7 downto 0) );
End counter;
Architecture art of counter is注意这里结构体名最好不要与实体名一致
Begin
Process(clk ,cw,increment,reset)
Variable i :std_logic_vector (7 downto 0);
Begin
If reset='1' then --复位不能用其上升沿,直接=1就可以了
i := "00000000";
elsIf(clk'event and clk = '1') then
If(increment = '1') then--这个使能位也一样,
If(cw = '1') then
i := i + 1;
elsIf(cw = '0') then
i := i - 1;
End if;
Else null;
End if;
End if;
led